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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9501 case MCK_SImm7s4: {
12045 case MCK_SImm7s4: return "MCK_SImm7s4";
16058 { 2583 /* ldnp */, AArch64::LDNPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
16060 { 2583 /* ldnp */, AArch64::LDNPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
16140 { 2640 /* ldp */, AArch64::LDPWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
16141 { 2640 /* ldp */, AArch64::LDPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
16144 { 2640 /* ldp */, AArch64::LDPSpost, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
16145 { 2640 /* ldp */, AArch64::LDPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
16150 { 2640 /* ldp */, AArch64::LDPWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
16152 { 2640 /* ldp */, AArch64::LDPSpre, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
16156 { 2644 /* ldpsw */, AArch64::LDPSWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
16157 { 2644 /* ldpsw */, AArch64::LDPSWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
16158 { 2644 /* ldpsw */, AArch64::LDPSWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
18707 { 5561 /* stnp */, AArch64::STNPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
18709 { 5561 /* stnp */, AArch64::STNPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
18769 { 5594 /* stp */, AArch64::STPWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
18770 { 5594 /* stp */, AArch64::STPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
18773 { 5594 /* stp */, AArch64::STPSpost, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
18774 { 5594 /* stp */, AArch64::STPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
18779 { 5594 /* stp */, AArch64::STPWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
18781 { 5594 /* stp */, AArch64::STPSpre, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
23416 { 2583 /* ldnp */, AArch64::LDNPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
23418 { 2583 /* ldnp */, AArch64::LDNPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
23498 { 2640 /* ldp */, AArch64::LDPWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
23499 { 2640 /* ldp */, AArch64::LDPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
23502 { 2640 /* ldp */, AArch64::LDPSpost, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
23503 { 2640 /* ldp */, AArch64::LDPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
23508 { 2640 /* ldp */, AArch64::LDPWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
23510 { 2640 /* ldp */, AArch64::LDPSpre, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
23514 { 2644 /* ldpsw */, AArch64::LDPSWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
23515 { 2644 /* ldpsw */, AArch64::LDPSWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
23516 { 2644 /* ldpsw */, AArch64::LDPSWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
26065 { 5561 /* stnp */, AArch64::STNPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
26067 { 5561 /* stnp */, AArch64::STNPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
26127 { 5594 /* stp */, AArch64::STPWpost, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
26128 { 5594 /* stp */, AArch64::STPWi, Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
26131 { 5594 /* stp */, AArch64::STPSpost, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_SImm7s4 }, },
26132 { 5594 /* stp */, AArch64::STPSi, Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_ }, },
26137 { 5594 /* stp */, AArch64::STPWpre, Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },
26139 { 5594 /* stp */, AArch64::STPSpre, Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4, AMFBS_None, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK__91_, MCK_GPR64sp, MCK_SImm7s4, MCK__93_, MCK__EXCLAIM_ }, },