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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10894 case MCK_SVEVectorList232: {
12220 case MCK_SVEVectorList232: return "MCK_SVEVectorList232";
15431 { 1998 /* ld2w */, AArch64::LD2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15432 { 1998 /* ld2w */, AArch64::LD2W, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
15433 { 1998 /* ld2w */, AArch64::LD2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
17413 { 4563 /* splice */, AArch64::SPLICE_ZPZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorList2321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorList232 }, },
18488 { 5282 /* st2w */, AArch64::ST2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18489 { 5282 /* st2w */, AArch64::ST2W, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
18490 { 5282 /* st2w */, AArch64::ST2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
19081 { 6111 /* tbl */, AArch64::TBL_ZZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorList2321_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorList232, MCK_SVEVectorSReg }, },
22789 { 1998 /* ld2w */, AArch64::LD2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22790 { 1998 /* ld2w */, AArch64::LD2W, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
22791 { 1998 /* ld2w */, AArch64::LD2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
24771 { 4563 /* splice */, AArch64::SPLICE_ZPZZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorList2321_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorList232 }, },
25846 { 5282 /* st2w */, AArch64::ST2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25847 { 5282 /* st2w */, AArch64::ST2W, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
25848 { 5282 /* st2w */, AArch64::ST2W_IMM, Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4, AMFBS_HasSVE, { MCK_SVEVectorList232, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
26439 { 6111 /* tbl */, AArch64::TBL_ZZZZ_S, Convert__SVEVectorSReg1_0__SVEVectorList2321_1__SVEVectorSReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEVectorList232, MCK_SVEVectorSReg }, },
32719 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
32721 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
32724 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
32727 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
32729 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
32731 { 1998 /* ld2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
36528 { 4563 /* splice */, 4 /* 2 */, MCK_SVEVectorList232, AMFBS_HasSVE2 },
36531 { 4563 /* splice */, 4 /* 2 */, MCK_SVEVectorList232, AMFBS_HasSVE2 },
38487 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
38489 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
38492 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
38495 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
38497 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
38499 { 5282 /* st2w */, 1 /* 0 */, MCK_SVEVectorList232, AMFBS_HasSVE },
39111 { 6111 /* tbl */, 2 /* 1 */, MCK_SVEVectorList232, AMFBS_HasSVE2 },
39113 { 6111 /* tbl */, 2 /* 1 */, MCK_SVEVectorList232, AMFBS_HasSVE2 },
40821 case MCK_SVEVectorList232: