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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13030 { 573 /* cinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
13404 { 861 /* cset */, AArch64::CSINCWr, Convert__Reg1_0__regWZR__regWZR__CondCode1_1, AMFBS_None, { MCK_GPR32, MCK_CondCode }, },
13408 { 872 /* csinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20388 { 573 /* cinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
20762 { 861 /* cset */, AArch64::CSINCWr, Convert__Reg1_0__regWZR__regWZR__CondCode1_1, AMFBS_None, { MCK_GPR32, MCK_CondCode }, },
20766 { 872 /* csinc */, AArch64::CSINCWr, Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_CondCode }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc15685 case AArch64::CSINCWr:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc16401 case AArch64::CSINCWr:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc92901 /*211403*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
92959 /*211530*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
92988 /*211586*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
93130 /*211881*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
93157 /*211937*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
96155 /*217757*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::CSINCWr), 0|OPFL_GlueInput,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9090 case AArch64::CSINCWr:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 290 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
298 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
lib/Target/AArch64/AArch64FastISel.cpp 2623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2628 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
3821 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
5138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr))
lib/Target/AArch64/AArch64InstrInfo.cpp 455 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
1317 case AArch64::CSINCWr:
4853 case AArch64::CSINCWr:
lib/Target/AArch64/AArch64InstructionSelector.cpp 1922 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
3372 .buildInstr(AArch64::CSINCWr, {DefReg}, {Register(AArch64::WZR), Register(AArch64::WZR)})