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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14277 { 1487 /* fmls */, AArch64::FMLSv1i32_indexed, Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4, AMFBS_HasNEON, { MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK_VectorReg128, MCK__DOT_s, MCK_IndexRange0_3 }, },
21646 { 1487 /* fmls */, AArch64::FMLSv1i32_indexed, Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4, AMFBS_HasNEON, { MCK__DOT_s, MCK_FPRAsmOperandFPR32, MCK_FPRAsmOperandFPR32, MCK_VectorReg128, MCK_IndexRange0_3 }, },
gen/lib/Target/AArch64/AArch64GenDAGISel.inc102025 /*228463*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102060 /*228534*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102082 /*228575*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102128 /*228658*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102171 /*228733*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102214 /*228810*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102257 /*228884*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102300 /*228960*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102342 /*229044*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102372 /*229106*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102436 /*229228*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
102462 /*229281*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::FMLSv1i32_indexed), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc39192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
39511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::FMLSv1i32_indexed,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc10467 case AArch64::FMLSv1i32_indexed:
lib/Target/AArch64/AArch64InstrInfo.cpp 4522 Opc = AArch64::FMLSv1i32_indexed;