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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15172 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15177 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15184 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_Imm0_31, MCK__93_ }, },
15194 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_Imm0_31, MCK__93_ }, },
22530 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
22535 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
22542 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_Imm0_31, MCK__93_ }, },
22552 { 1951 /* ld1sb */, AArch64::GLD1SB_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_Imm0_31, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16629 case AArch64::GLD1SB_S_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17345 case AArch64::GLD1SB_S_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 7323 case AArch64::GLD1SB_S_IMM_REAL: