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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15207 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15211 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15219 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s2, MCK__93_ }, },
15233 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s2, MCK__93_ }, },
22565 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
22569 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
22577 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s2, MCK__93_ }, },
22591 { 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s2, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16661 case AArch64::GLD1SH_S_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17377 case AArch64::GLD1SH_S_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 7325 case AArch64::GLD1SH_S_IMM_REAL: