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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14929 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14930 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14961 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
14962 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
22287 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22288 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22319 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
22320 { 1858 /* ld1b */, AArch64::LD1B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17316 case AArch64::LD1B_IMM:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18032 case AArch64::LD1B_IMM:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc111864 /*249720*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::LD1B_IMM), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6435 case AArch64::LD1B_IMM: