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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14772 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14773 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14840 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_16b, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14841 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_16b, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22130 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22131 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22198 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_16b, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22199 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_16b, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17364 case AArch64::LD1Fourv16b_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18080 case AArch64::LD1Fourv16b_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12702 case AArch64::LD1Fourv16b_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 444 case AArch64::LD1Fourv16b_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3740 SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 430 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },