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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14810 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
14811 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14852 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
14853 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22168 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22169 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22210 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22211 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18153 case AArch64::LD1Threev1d_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18869 case AArch64::LD1Threev1d_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12727 case AArch64::LD1Threev1d_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 429 case AArch64::LD1Threev1d_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3643 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
3727 SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 421 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },