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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14816 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
14817 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14876 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4h, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
14877 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4h, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22174 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22175 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22234 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4h, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22235 { 1854 /* ld1 */, AArch64::LD1Threev4h_POST, Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4h, MCK_VecListThree64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18192 case AArch64::LD1Threev4h_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18908 case AArch64::LD1Threev4h_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12730 case AArch64::LD1Threev4h_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 431 case AArch64::LD1Threev4h_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3715 SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 419 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },