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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14838 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14839 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14902 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14903 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22196 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22197 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22260 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22261 { 1854 /* ld1 */, AArch64::LD1Twov8h_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18335 case AArch64::LD1Twov8h_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc19051 case AArch64::LD1Twov8h_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12741 case AArch64::LD1Twov8h_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 427 case AArch64::LD1Twov8h_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3690 SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 399 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },