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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14914 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
14915 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList1_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14922 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListOne128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
14923 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListOne128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22272 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
22273 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList1_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22280 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListOne128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
22281 { 1854 /* ld1 */, AArch64::LD1i32_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListOne128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18393 case AArch64::LD1i32_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc19109 case AArch64::LD1i32_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc13030 case AArch64::LD1i32_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 381 case AArch64::LD1i32_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3885 SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 356 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },