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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15364 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15365 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList2_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15372 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListTwo128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15373 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListTwo128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22722 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22723 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList2_032, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22730 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListTwo128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22731 { 1974 /* ld2 */, AArch64::LD2i32_POST, Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_s, MCK_VecListTwo128, MCK_IndexRange0_3, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18704 case AArch64::LD2i32_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc19420 case AArch64::LD2i32_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc13031 case AArch64::LD2i32_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 384 case AArch64::LD2i32_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3904 SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 444 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },