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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15612 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15613 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList4_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15620 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListFour128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15621 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListFour128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22970 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22971 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList4_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22978 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListFour128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22979 { 2032 /* ld4 */, AArch64::LD4i64_POST, Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListFour128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc19339 case AArch64::LD4i64_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc20055 case AArch64::LD4i64_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc13105 case AArch64::LD4i64_POST: {
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 392 case AArch64::LD4i64_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3946 SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 521 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },