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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15860 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15865 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15870 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
15880 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
23218 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23223 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23228 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
23238 { 2471 /* ldff1sb */, AArch64::LDFF1SB_H_REAL, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc19938 case AArch64::LDFF1SB_H_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc20654 case AArch64::LDFF1SB_H_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15251 case AArch64::LDFF1SB_H_REAL: