|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16089 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
16092 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
16095 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
16098 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
23447 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23450 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23453 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
23456 { 2602 /* ldnt1h */, AArch64::LDNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc20481 case AArch64::LDNT1H_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc21197 case AArch64::LDNT1H_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6199 case AArch64::LDNT1H_ZZR_D_REAL: