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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16109 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
16111 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
16113 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
16115 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23467 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
23469 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
23471 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
23473 { 2617 /* ldnt1sh */, AArch64::LDNT1SH_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc20556 case AArch64::LDNT1SH_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc21272 case AArch64::LDNT1SH_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6204 case AArch64::LDNT1SH_ZZR_S_REAL: