|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16445 { 3314 /* lsr */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16471 { 3323 /* lsrv */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
23803 { 3314 /* lsr */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
23829 { 3323 /* lsrv */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
gen/lib/Target/AArch64/AArch64GenDAGISel.inc95202 /*215963*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::LSRVWr), 0,
95221 /*216006*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::LSRVWr), 0,
95230 /*216024*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::LSRVWr), 0,
95257 /*216087*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::LSRVWr), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc37683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
37699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
37715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::LSRVWr,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 8635 case AArch64::LSRVWr:
lib/Target/AArch64/AArch64FastISel.cpp 4192 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
4193 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
4194 case MVT::i32: Opc = AArch64::LSRVWr; break;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2504 Opc = (VT == MVT::i32) ? AArch64::LSRVWr : AArch64::LSRVXr;
lib/Target/AArch64/AArch64InstructionSelector.cpp 457 return AArch64::LSRVWr;