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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16519 { 3356 /* mov */, AArch64::ORRWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
16778 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16794 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
23877 { 3356 /* mov */, AArch64::ORRWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
24136 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
24158 { 3495 /* orr */, AArch64::ORRWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc22185 case AArch64::ORRWrs:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc22901 case AArch64::ORRWrs:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc89002 /*204630*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORRWrs), 0,
89008 /*204643*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORRWrs), 0,
96334 /*218084*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORRWrs), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 6275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs,
6289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRWrs,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18106 case AArch64::ORRWrs:
18163 case AArch64::ORRWrs:
18295 case AArch64::ORRWrs:
18392 case AArch64::ORRWrs:
29844 case AArch64::ORRWrs:
29901 case AArch64::ORRWrs:
30033 case AArch64::ORRWrs:
30130 case AArch64::ORRWrs:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15472 case AArch64::ORRWrs:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 462 case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
lib/Target/AArch64/AArch64FastISel.cpp 1745 { AArch64::ORRWrs, AArch64::ORRXrs },
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2050 case AArch64::ORRWrs:
lib/Target/AArch64/AArch64InstrInfo.cpp 2633 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs,
5711 if (MI.getOpcode() == AArch64::ORRWrs &&
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 979 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
lib/Target/AArch64/AArch64MacroFusion.cpp 311 case AArch64::ORRWrs:
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 958 case AArch64::ORRWrs: