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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16764 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
16765 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
16766 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
16767 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
16787 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
16789 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
16790 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
16793 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
24122 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
24123 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
24124 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
24125 { 3486 /* orn */, AArch64::ORR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
24145 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
24147 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
24148 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
24151 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc22255 case AArch64::ORR_ZI:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc22971 case AArch64::ORR_ZI:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15149 case AArch64::ORR_ZI: {