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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 7745 { 898, 3, 1, 4, 424, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #898 = FABD32
7767 { 920, 3, 1, 4, 432, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #920 = FACGE32
7778 { 931, 3, 1, 4, 432, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #931 = FACGT32
7804 { 957, 3, 1, 4, 423, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #957 = FADDSrr
7837 { 990, 3, 1, 4, 470, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #990 = FCMEQ32
7859 { 1012, 3, 1, 4, 471, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1012 = FCMGE32
7881 { 1034, 3, 1, 4, 470, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1034 = FCMGT32
8180 { 1333, 3, 1, 4, 111, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1333 = FDIVSrr
8220 { 1373, 3, 1, 4, 435, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1373 = FMAXNMSrr
8249 { 1402, 3, 1, 4, 435, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1402 = FMAXSrr
8282 { 1435, 3, 1, 4, 435, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1435 = FMINNMSrr
8311 { 1464, 3, 1, 4, 435, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1464 = FMINSrr
8423 { 1576, 3, 1, 4, 634, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1576 = FMULSrr
8425 { 1578, 3, 1, 4, 477, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1578 = FMULX32
8499 { 1652, 3, 1, 4, 634, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1652 = FNMULSrr
8512 { 1665, 3, 1, 4, 599, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1665 = FRECPS32
8637 { 1790, 3, 1, 4, 276, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1790 = FRSQRTS32
8669 { 1822, 3, 1, 4, 423, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1822 = FSUBSrr
10350 { 3503, 3, 1, 4, 512, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3503 = SQADDv1i32
10444 { 3597, 3, 1, 4, 446, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3597 = SQDMULHv1i32
10566 { 3719, 3, 1, 4, 446, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3719 = SQRDMULHv1i32
10586 { 3739, 3, 1, 4, 442, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3739 = SQRSHLv1i32
10659 { 3812, 3, 1, 4, 237, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3812 = SQSHLv1i32
10722 { 3875, 3, 1, 4, 516, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #3875 = SQSUBv1i32
11757 { 4910, 3, 1, 4, 512, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #4910 = UQADDv1i32
11820 { 4973, 3, 1, 4, 442, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #4973 = UQRSHLv1i32
11863 { 5016, 3, 1, 4, 237, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #5016 = UQSHLv1i32
11911 { 5064, 3, 1, 4, 516, 0, 0x1ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #5064 = UQSUBv1i32