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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 9902 { 3055, 4, 1, 4, 443, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3055 = RSHRNv16i8_shift
9905 { 3058, 4, 1, 4, 443, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3058 = RSHRNv4i32_shift
9906 { 3059, 4, 1, 4, 443, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3059 = RSHRNv8i16_shift
10126 { 3279, 4, 1, 4, 444, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3279 = SHRNv16i8_shift
10129 { 3282, 4, 1, 4, 444, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3282 = SHRNv4i32_shift
10130 { 3283, 4, 1, 4, 444, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3283 = SHRNv8i16_shift
10151 { 3304, 4, 1, 4, 549, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3304 = SLIv16i8_shift
10153 { 3306, 4, 1, 4, 549, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3306 = SLIv2i64_shift
10155 { 3308, 4, 1, 4, 549, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3308 = SLIv4i32_shift
10156 { 3309, 4, 1, 4, 549, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3309 = SLIv8i16_shift
10604 { 3757, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3757 = SQRSHRNv16i8_shift
10607 { 3760, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3760 = SQRSHRNv4i32_shift
10608 { 3761, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3761 = SQRSHRNv8i16_shift
10619 { 3772, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3772 = SQRSHRUNv16i8_shift
10622 { 3775, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3775 = SQRSHRUNv4i32_shift
10623 { 3776, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3776 = SQRSHRUNv8i16_shift
10683 { 3836, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3836 = SQSHRNv16i8_shift
10686 { 3839, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3839 = SQSHRNv4i32_shift
10687 { 3840, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3840 = SQSHRNv8i16_shift
10698 { 3851, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3851 = SQSHRUNv16i8_shift
10701 { 3854, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3854 = SQSHRUNv4i32_shift
10702 { 3855, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3855 = SQSHRUNv8i16_shift
10776 { 3929, 4, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3929 = SRIv16i8_shift
10778 { 3931, 4, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3931 = SRIv2i64_shift
10780 { 3933, 4, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3933 = SRIv4i32_shift
10781 { 3934, 4, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3934 = SRIv8i16_shift
10816 { 3969, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3969 = SRSRAv16i8_shift
10818 { 3971, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3971 = SRSRAv2i64_shift
10820 { 3973, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3973 = SRSRAv4i32_shift
10821 { 3974, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #3974 = SRSRAv8i16_shift
10856 { 4009, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4009 = SSRAv16i8_shift
10858 { 4011, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4011 = SSRAv2i64_shift
10860 { 4013, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4013 = SSRAv4i32_shift
10861 { 4014, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4014 = SSRAv8i16_shift
11838 { 4991, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4991 = UQRSHRNv16i8_shift
11841 { 4994, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4994 = UQRSHRNv4i32_shift
11842 { 4995, 4, 1, 4, 782, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #4995 = UQRSHRNv8i16_shift
11887 { 5040, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5040 = UQSHRNv16i8_shift
11890 { 5043, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5043 = UQSHRNv4i32_shift
11891 { 5044, 4, 1, 4, 703, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5044 = UQSHRNv8i16_shift
11984 { 5137, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5137 = URSRAv16i8_shift
11986 { 5139, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5139 = URSRAv2i64_shift
11988 { 5141, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5141 = URSRAv4i32_shift
11989 { 5142, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5142 = URSRAv8i16_shift
12039 { 5192, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5192 = USRAv16i8_shift
12041 { 5194, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5194 = USRAv2i64_shift
12043 { 5196, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5196 = USRAv4i32_shift
12044 { 5197, 4, 1, 4, 438, 0, 0x1ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #5197 = USRAv8i16_shift