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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc18752 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
18755 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
18758 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
18761 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
26110 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
26113 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
26116 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
26119 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25115 case AArch64::STNT1W_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc25831 case AArch64::STNT1W_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6213 case AArch64::STNT1W_ZZR_D_REAL: