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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13217 { 665 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
13223 { 665 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
16739 { 3443 /* negs */, AArch64::SUBSWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
16741 { 3443 /* negs */, AArch64::SUBSWrs, Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
19000 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
19007 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
20575 { 665 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
20581 { 665 /* cmp */, AArch64::SUBSWrs, Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
24097 { 3443 /* negs */, AArch64::SUBSWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
24099 { 3443 /* negs */, AArch64::SUBSWrs, Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
26358 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
26365 { 5976 /* subs */, AArch64::SUBSWrs, Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_ArithmeticShifter32 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25725 case AArch64::SUBSWrs:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc26441 case AArch64::SUBSWrs:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc86906 /*200597*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::SUBSWrs), 0,
93535 /*212816*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::SUBSWrs), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 4142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SUBSWrs,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18037 case AArch64::SUBSWrs:
18376 case AArch64::SUBSWrs:
29775 case AArch64::SUBSWrs:
30114 case AArch64::SUBSWrs:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15474 case AArch64::SUBSWrs:
lib/Target/AArch64/AArch64AsmPrinter.cpp 361 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
lib/Target/AArch64/AArch64CondBrTuning.cpp 180 case AArch64::SUBSWrs:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 445 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
642 AArch64::SUBSWrs,
lib/Target/AArch64/AArch64FastISel.cpp 1417 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
5101 CmpOpc = AArch64::SUBSWrs;
lib/Target/AArch64/AArch64InstrInfo.cpp 798 case AArch64::SUBSWrs: {
999 case AArch64::SUBSWrs:
1118 case AArch64::SUBSWrs:
1119 return MIDefinesZeroReg ? AArch64::SUBSWrs : AArch64::SUBWrs;
1878 return AArch64::SUBSWrs;
lib/Target/AArch64/AArch64MacroFusion.cpp 52 case AArch64::SUBSWrs:
240 case AArch64::SUBSWrs:
334 case AArch64::SUBSWrs:
347 case AArch64::SUBSWrs:
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 246 case AArch64::SUBSWrs:
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 949 case AArch64::SUBSWrs: