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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc98520 /*222020*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98531 /*222045*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98542 /*222070*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98553 /*222095*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98564 /*222120*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98578 /*222151*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98589 /*222176*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98600 /*222201*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98611 /*222226*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98622 /*222251*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98636 /*222282*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98647 /*222307*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98658 /*222332*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98669 /*222357*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
98680 /*222382*/ OPC_EmitNode1, TARGET_VAL(AArch64::SUBWrr), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc18602 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18628 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18654 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18732 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18758 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18784 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18810 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18862 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18888 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18914 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18940 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
18966 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::SUBWrr,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18054 case AArch64::SUBWrr:
29792 case AArch64::SUBWrr:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 5486 case AArch64::SUBWrr:
lib/Target/AArch64/AArch64CondBrTuning.cpp 164 case AArch64::SUBWrr:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 413 case AArch64::SUBWrr:
441 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
lib/Target/AArch64/AArch64FastISel.cpp 1328 { { AArch64::SUBWrr, AArch64::SUBXrr },
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2551 NegOpc = AArch64::SUBWrr;
lib/Target/AArch64/AArch64InstrInfo.cpp 477 case AArch64::SUBWrr: {
1115 return AArch64::SUBWrr;
1253 case AArch64::SUBWrr:
1873 case AArch64::SUBWrr:
3525 case AArch64::SUBWrr:
3708 case AArch64::SUBWrr:
4201 SubOpc = AArch64::SUBWrr;
lib/Target/AArch64/AArch64MacroFusion.cpp 94 case AArch64::SUBWrr:
282 case AArch64::SUBWrr:
323 case AArch64::SUBWrr:
357 case AArch64::SUBWrr: