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References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
16448   { 3314 /* lsr */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63 }, },
19264   { 6320 /* ubfm */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63, MCK_Imm0_63 }, },
19866   { 6893 /* uxtb */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
19871   { 6898 /* uxth */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
19886   { 6914 /* uxtw */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
23806   { 3314 /* lsr */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63 }, },
26622   { 6320 /* ubfm */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_Imm0_63, MCK_Imm0_63 }, },
27224   { 6893 /* uxtb */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
27229   { 6898 /* uxth */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
27244   { 6914 /* uxtw */, AArch64::UBFMXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc
26116   case AArch64::UBFMXri:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
26832   case AArch64::UBFMXri:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc
70441 /*168932*/            OPC_EmitNode1, TARGET_VAL(AArch64::UBFMXri), 0,
94909 /*215416*/          OPC_MorphNodeTo1, TARGET_VAL(AArch64::UBFMXri), 0,
95190 /*215940*/        OPC_MorphNodeTo1, TARGET_VAL(AArch64::UBFMXri), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc
37741         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::UBFMXri,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
 9898     case AArch64::UBFMXri: {
lib/Target/AArch64/AArch64AsmPrinter.cpp
  300     OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri)
lib/Target/AArch64/AArch64FastISel.cpp
 4169     {AArch64::UBFMWri, AArch64::UBFMXri}
 4290     {AArch64::UBFMWri, AArch64::UBFMXri}
 4399     {AArch64::UBFMWri, AArch64::UBFMXri}
 4439       Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
 4446       Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
 4453     Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
 1622   Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
 1695       Opc = AArch64::UBFMXri;
 1768     Opc = N->getOpcode() == ISD::SRA ? AArch64::SBFMXri : AArch64::UBFMXri;
 1826   case AArch64::UBFMXri:
 1848   if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
 2047   case AArch64::UBFMXri:
 2110   unsigned UBFMOpc = BitWidth == 32 ? AArch64::UBFMWri : AArch64::UBFMXri;
 2331       if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
 2420     unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
 2485   unsigned Opc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri;
lib/Target/AArch64/AArch64InstrInfo.cpp
  918   case AArch64::UBFMXri: // aka uxtw
lib/Target/AArch64/AArch64InstructionSelector.cpp
 1221       MIB.buildInstr(Is64Bit ? AArch64::UBFMXri : AArch64::UBFMWri,
 1618     I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
 2109       ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMXri : AArch64::UBFMXri,
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
 1027                   TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
   74       Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
   81     bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
  126       } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
  133       } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {