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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc11434 case AArch64::Z0: OpKind = MCK_ZPR_3b; break;
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 161 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
1171 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 2670 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31,
2690 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
2700 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
3630 { 96U, AArch64::Z0 },
3747 { 96U, AArch64::Z0 },
4026 { AArch64::Z0, 96U },
4305 { AArch64::Z0, 96U },
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1465 Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1503 /* ZReg */ { AArch64::Z0,
1504 AArch64::Z0, AArch64::Z0_Z1,
2187 .Case("z0", AArch64::Z0)
3876 assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31));
3877 return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) ||
3878 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) ||
3879 (ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) ||
3880 (ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) ||
3881 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) ||
3882 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0));
3882 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0));
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 496 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3,
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 1193 case AArch64::Z0: Reg = AArch64::Z1; break;
1226 Reg = AArch64::Z0;
1570 O << getRegisterName(Reg - AArch64::Z0 + Base);