|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12369 if ((FB[AArch64::FeatureMTE]))
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17269 STI.getFeatureBits()[AArch64::FeatureMTE]) {
20051 STI.getFeatureBits()[AArch64::FeatureMTE]) {
24220 STI.getFeatureBits()[AArch64::FeatureMTE]) {
24823 STI.getFeatureBits()[AArch64::FeatureMTE]) {
24839 STI.getFeatureBits()[AArch64::FeatureMTE]) {
25695 STI.getFeatureBits()[AArch64::FeatureMTE]) {
25709 STI.getFeatureBits()[AArch64::FeatureMTE]) {
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17985 STI.getFeatureBits()[AArch64::FeatureMTE]) {
20767 STI.getFeatureBits()[AArch64::FeatureMTE]) {
24936 STI.getFeatureBits()[AArch64::FeatureMTE]) {
25539 STI.getFeatureBits()[AArch64::FeatureMTE]) {
25555 STI.getFeatureBits()[AArch64::FeatureMTE]) {
26411 STI.getFeatureBits()[AArch64::FeatureMTE]) {
26425 STI.getFeatureBits()[AArch64::FeatureMTE]) {
gen/lib/Target/AArch64/AArch64GenDisassemblerTables.inc20586 return (Bits[AArch64::FeatureMTE]);
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15835 if ((FB[AArch64::FeatureMTE]))
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc 247 { "mte", "Enable Memory Tagging Extension", AArch64::FeatureMTE, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
17849 if (Bits[AArch64::FeatureMTE]) HasMTE = true;
gen/lib/Target/AArch64/AArch64GenSystemOperands.inc 1350 { "IGVAC", 0x3B3, {AArch64::FeatureMTE} }, // 10
1351 { "IGSW", 0x3B4, {AArch64::FeatureMTE} }, // 11
1352 { "CGSW", 0x3D4, {AArch64::FeatureMTE} }, // 12
1353 { "CIGSW", 0x3F4, {AArch64::FeatureMTE} }, // 13
1354 { "CGVAC", 0x1BD3, {AArch64::FeatureMTE} }, // 14
1355 { "CGVAP", 0x1BE3, {AArch64::FeatureMTE} }, // 15
1356 { "CGVADP", 0x1BEB, {AArch64::FeatureMTE} }, // 16
1357 { "CIGVAC", 0x1BF3, {AArch64::FeatureMTE} }, // 17
1358 { "GVA", 0x1BA3, {AArch64::FeatureMTE} }, // 18
1359 { "IGDVAC", 0x3B5, {AArch64::FeatureMTE} }, // 19
1360 { "IGDSW", 0x3B6, {AArch64::FeatureMTE} }, // 20
1361 { "CGDSW", 0x3D6, {AArch64::FeatureMTE} }, // 21
1362 { "CIGDSW", 0x3F6, {AArch64::FeatureMTE} }, // 22
1363 { "CGDVAC", 0x1BD5, {AArch64::FeatureMTE} }, // 23
1364 { "CGDVAP", 0x1BE5, {AArch64::FeatureMTE} }, // 24
1365 { "CGDVADP", 0x1BED, {AArch64::FeatureMTE} }, // 25
1366 { "CIGDVAC", 0x1BF5, {AArch64::FeatureMTE} }, // 26
1367 { "GZVA", 0x1BA4, {AArch64::FeatureMTE} }, // 27
1955 { "TCO", 0x1C, {AArch64::FeatureMTE} }, // 7
3001 { "TCO", 0xDA17, true, true, {AArch64::FeatureMTE} }, // 747
3002 { "GCR_EL1", 0xC086, true, true, {AArch64::FeatureMTE} }, // 748
3003 { "RGSR_EL1", 0xC085, true, true, {AArch64::FeatureMTE} }, // 749
3004 { "TFSR_EL1", 0xC2B0, true, true, {AArch64::FeatureMTE} }, // 750
3005 { "TFSR_EL2", 0xE2B0, true, true, {AArch64::FeatureMTE} }, // 751
3006 { "TFSR_EL3", 0xF2B0, true, true, {AArch64::FeatureMTE} }, // 752
3007 { "TFSR_EL12", 0xEAB0, true, true, {AArch64::FeatureMTE} }, // 753
3008 { "TFSRE0_EL1", 0xC2B1, true, true, {AArch64::FeatureMTE} }, // 754
3009 { "GMID_EL1", 0xC804, true, false, {AArch64::FeatureMTE} }, // 755
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 2820 {"mte", {AArch64::FeatureMTE}},