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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6406 { 573, 2, 0, 2, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #573 = tBX_RET
6462 { 629, 2, 0, 4, 851, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #629 = BX_RET
6493 { 660, 2, 0, 4, 841, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList10, OperandInfo116, -1 ,nullptr }, // Inst #660 = ERET
6500 { 667, 2, 0, 4, 584, 0|(1ULL<<MCID::Predicable), 0x8c00ULL, ImplicitList11, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #667 = FMSTAT
6584 { 751, 2, 0, 4, 880, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #751 = MOVPCLR
6609 { 776, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #776 = MVE_LCTP
9600 { 3767, 2, 0, 4, 1019, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #3767 = t2CLREX
9623 { 3790, 2, 0, 4, 841, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #3790 = t2DCPS1
9624 { 3791, 2, 0, 4, 841, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #3791 = t2DCPS2
9625 { 3792, 2, 0, 4, 841, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #3792 = t2DCPS3
9794 { 3961, 2, 0, 4, 841, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #3961 = t2SG