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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8015 { 2182, 5, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2182 = VCVTf2xsq
8017 { 2184, 5, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2184 = VCVTf2xuq
8024 { 2191, 5, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2191 = VCVTh2xsq
8026 { 2193, 5, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2193 = VCVTh2xuq
8036 { 2203, 5, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2203 = VCVTxs2fq
8038 { 2205, 5, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2205 = VCVTxs2hq
8040 { 2207, 5, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2207 = VCVTxu2fq
8042 { 2209, 5, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2209 = VCVTxu2hq
9025 { 3192, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3192 = VRSHRsv16i8
9028 { 3195, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3195 = VRSHRsv2i64
9030 { 3197, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3197 = VRSHRsv4i32
9031 { 3198, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3198 = VRSHRsv8i16
9033 { 3200, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3200 = VRSHRuv16i8
9036 { 3203, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3203 = VRSHRuv2i64
9038 { 3205, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3205 = VRSHRuv4i32
9039 { 3206, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3206 = VRSHRuv8i16
9127 { 3294, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3294 = VSHRsv16i8
9130 { 3297, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3297 = VSHRsv2i64
9132 { 3299, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3299 = VSHRsv4i32
9133 { 3300, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3300 = VSHRsv8i16
9135 { 3302, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3302 = VSHRuv16i8
9138 { 3305, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3305 = VSHRuv2i64
9140 { 3307, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3307 = VSHRuv4i32
9141 { 3308, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #3308 = VSHRuv8i16