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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8321 { 2488, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2488 = VLD3DUPd16_UPD
8325 { 2492, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2492 = VLD3DUPd32_UPD
8329 { 2496, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2496 = VLD3DUPd8_UPD
8333 { 2500, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2500 = VLD3DUPq16_UPD
8337 { 2504, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2504 = VLD3DUPq32_UPD
8341 { 2508, 9, 4, 4, 629, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2508 = VLD3DUPq8_UPD
8365 { 2532, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2532 = VLD3d16_UPD
8369 { 2536, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2536 = VLD3d32_UPD
8373 { 2540, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2540 = VLD3d8_UPD
8376 { 2543, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2543 = VLD3q16_UPD
8381 { 2548, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2548 = VLD3q32_UPD
8386 { 2553, 9, 4, 4, 609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2553 = VLD3q8_UPD