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References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
10499   { 331 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11674   { 2028 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11689   { 2028 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc
41972 /* 92479*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::VADDD), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc
 3612     return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc
25309       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc
13656     case ARM::VADDD:
lib/Target/ARM/ARMBaseInstrInfo.cpp
   91   { ARM::VMLAD,       ARM::VMULD,       ARM::VADDD,      false,  false },
lib/Target/ARM/ARMFastISel.cpp
 1813       Opc = is64bit ? ARM::VADDD : ARM::VADDS;