|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc14118 { 3383 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc39566 /* 86945*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
39656 /* 87122*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
39731 /* 87262*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
39821 /* 87439*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
39884 /* 87563*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
39986 /* 87756*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
40049 /* 87880*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
40151 /* 88073*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
53196 /*118875*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV32q16), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 450 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
981 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1001 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1088 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1108 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1302 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1322 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1409 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1429 return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 9943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
9959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
10919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9701 case ARM::VREV32q16: