reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 3612   extern const TargetRegisterClass rGPRRegClass;

References

gen/lib/Target/ARM/ARMGenFastISel.inc

  182     return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
  203     return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
  224     return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
  368     return fastEmitInst_r(ARM::VMOVRH, &ARM::rGPRRegClass, Op0, Op0IsKill);
 1544     return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
 1589     return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
 1633     return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
 2880     return fastEmitInst_rr(ARM::t2QADD16, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2901     return fastEmitInst_rr(ARM::t2QADD8, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2922     return fastEmitInst_rr(ARM::t2QSUB16, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2943     return fastEmitInst_rr(ARM::t2QSUB8, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2964     return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 2985     return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3006     return fastEmitInst_rr(ARM::t2SUBSrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 3517     return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4148     return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4244     return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4265     return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4342     return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4363     return fastEmitInst_rr(ARM::t2QADD, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4414     return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4435     return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4610     return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4631     return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4652     return fastEmitInst_rr(ARM::t2QSUB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 4854     return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 5067     return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 5301     return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_s8, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 5319     return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_s16, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 5349     return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_u8, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 5367     return fastEmitInst_ri(ARM::MVE_VMOV_from_lane_u16, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6612     return fastEmitInst_ri(ARM::t2SUBSri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6648     return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6666     return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6702     return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6782     return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 6863     return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
 7428     return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 4968   &ARM::rGPRRegClass,
 4980   &ARM::rGPRRegClass,
 5000   &ARM::rGPRRegClass,
 5013   &ARM::rGPRRegClass,
 5024   &ARM::rGPRRegClass,
 5035   &ARM::rGPRRegClass,
 5050   &ARM::rGPRRegClass,
 5064   &ARM::rGPRRegClass,
 5078   &ARM::rGPRRegClass,
 5092   &ARM::rGPRRegClass,
 5105   &ARM::rGPRRegClass,
 5120   &ARM::rGPRRegClass,
 5138   &ARM::rGPRRegClass,
 5155   &ARM::rGPRRegClass,
 5193   &ARM::rGPRRegClass,
 8024     &ARM::rGPRRegClass,

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  259     return &ARM::rGPRRegClass;  // Can't copy CCR registers.

lib/Target/ARM/ARMFastISel.cpp

  473     const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
  489       const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
  546   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
  940       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  955       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  969       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
  978         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
 1485   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
 1662     RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
 2624     /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
 2967   Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
 3055   const TargetRegisterClass *RC = &ARM::rGPRRegClass;

lib/Target/ARM/ARMISelLowering.cpp

10301     Register Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
10630         isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);