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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 8152 { 0 /* */, Hexagon::A2_addi, Convert__Reg1_0__Reg1_4__s32_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_s32_0Imm, MCK__41_ }, },
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc14745 /* 28014*/ OPC_EmitNode1, TARGET_VAL(Hexagon::A2_addi), 0,
25639 /* 49222*/ OPC_MorphNodeTo1, TARGET_VAL(Hexagon::A2_addi), 0,
25645 /* 49234*/ OPC_MorphNodeTo1, TARGET_VAL(Hexagon::A2_addi), 0,
32980 /* 63749*/ OPC_MorphNodeTo1, TARGET_VAL(Hexagon::A2_addi), 0,
32987 /* 63761*/ OPC_MorphNodeTo1, TARGET_VAL(Hexagon::A2_addi), 0,
65565 /*126175*/ OPC_MorphNodeTo1, TARGET_VAL(Hexagon::A2_addi), 0,
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc17556 { Hexagon::A2_addi, Hexagon::A2_paddit, Hexagon::A2_paddif },
17737 { Hexagon::A2_addi, Hexagon::A2_add },
gen/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc 5210 case Hexagon::A2_addi: {
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 1314 Inst.setOpcode(Hexagon::A2_addi);
lib/Target/Hexagon/HexagonAsmPrinter.cpp 278 Inst.setOpcode(Hexagon::A2_addi);
lib/Target/Hexagon/HexagonBitTracker.cpp 380 case A2_addi:
lib/Target/Hexagon/HexagonConstExtenders.cpp 856 case Hexagon::A2_addi:
869 case A2_tfrsi: return A2_addi;
966 case Hexagon::A2_addi: return Hexagon::A2_add;
1054 if (Opc == Hexagon::A2_addi) {
1106 case Hexagon::A2_addi: // s16
1194 case Hexagon::A2_addi: // (Rd: ## + Rs<<0)
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1718 assert(IdxOpc == Hexagon::A2_addi);
1753 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) {
1758 bool IsAddi = ExtOpc == Hexagon::A2_addi;
lib/Target/Hexagon/HexagonFrameLowering.cpp 640 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
659 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
762 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
2382 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 911 TII->get(Hexagon::A2_addi));
929 if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
954 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
1788 nonIndI->getOpcode() == Hexagon::A2_addi &&
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 173 MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
545 MachineSDNode *A = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
lib/Target/Hexagon/HexagonInstrInfo.cpp 744 TII->get(Hexagon::A2_addi), NewLoopCount)
1937 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2751 case Hexagon::A2_addi:
3942 case Hexagon::A2_addi:
lib/Target/Hexagon/HexagonOptAddrMode.cpp 697 (MI->getOpcode() != Hexagon::A2_addi ||
721 if (MI->getOpcode() == Hexagon::A2_addi) {
lib/Target/Hexagon/HexagonRDFOpt.cpp 130 case Hexagon::A2_addi: {
lib/Target/Hexagon/HexagonRegisterInfo.cpp 206 MI.setDesc(HII.get(Hexagon::A2_addi));
212 MI.setDesc(HII.get(Hexagon::A2_addi));
222 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
lib/Target/Hexagon/HexagonSplitDouble.cpp 679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 415 case Hexagon::A2_addi:
544 case Hexagon::A2_addi:
589 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
711 case Hexagon::A2_addi: