|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 5180 { 1550, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1550 = M2_cmaci_s0
5181 { 1551, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1551 = M2_cmacr_s0
5182 { 1552, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1552 = M2_cmacs_s0
5183 { 1553, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1553 = M2_cmacs_s1
5184 { 1554, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1554 = M2_cmacsc_s0
5185 { 1555, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1555 = M2_cmacsc_s1
5196 { 1566, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1566 = M2_cnacs_s0
5197 { 1567, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1567 = M2_cnacs_s1
5198 { 1568, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1568 = M2_cnacsc_s0
5199 { 1569, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1569 = M2_cnacsc_s1
5200 { 1570, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1570 = M2_dpmpyss_acc_s0
5201 { 1571, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1571 = M2_dpmpyss_nac_s0
5204 { 1574, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1574 = M2_dpmpyuu_acc_s0
5205 { 1575, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1575 = M2_dpmpyuu_nac_s0
5314 { 1684, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1684 = M2_mpyd_acc_hh_s0
5315 { 1685, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1685 = M2_mpyd_acc_hh_s1
5316 { 1686, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1686 = M2_mpyd_acc_hl_s0
5317 { 1687, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1687 = M2_mpyd_acc_hl_s1
5318 { 1688, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1688 = M2_mpyd_acc_lh_s0
5319 { 1689, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1689 = M2_mpyd_acc_lh_s1
5320 { 1690, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1690 = M2_mpyd_acc_ll_s0
5321 { 1691, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1691 = M2_mpyd_acc_ll_s1
5330 { 1700, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1700 = M2_mpyd_nac_hh_s0
5331 { 1701, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1701 = M2_mpyd_nac_hh_s1
5332 { 1702, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1702 = M2_mpyd_nac_hl_s0
5333 { 1703, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1703 = M2_mpyd_nac_hl_s1
5334 { 1704, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1704 = M2_mpyd_nac_lh_s0
5335 { 1705, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1705 = M2_mpyd_nac_lh_s1
5336 { 1706, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1706 = M2_mpyd_nac_ll_s0
5337 { 1707, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1707 = M2_mpyd_nac_ll_s1
5375 { 1745, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1745 = M2_mpyud_acc_hh_s0
5376 { 1746, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1746 = M2_mpyud_acc_hh_s1
5377 { 1747, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1747 = M2_mpyud_acc_hl_s0
5378 { 1748, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1748 = M2_mpyud_acc_hl_s1
5379 { 1749, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1749 = M2_mpyud_acc_lh_s0
5380 { 1750, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1750 = M2_mpyud_acc_lh_s1
5381 { 1751, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1751 = M2_mpyud_acc_ll_s0
5382 { 1752, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1752 = M2_mpyud_acc_ll_s1
5391 { 1761, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1761 = M2_mpyud_nac_hh_s0
5392 { 1762, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1762 = M2_mpyud_nac_hh_s1
5393 { 1763, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1763 = M2_mpyud_nac_hl_s0
5394 { 1764, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1764 = M2_mpyud_nac_hl_s1
5395 { 1765, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1765 = M2_mpyud_nac_lh_s0
5396 { 1766, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1766 = M2_mpyud_nac_lh_s1
5397 { 1767, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1767 = M2_mpyud_nac_ll_s0
5398 { 1768, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1768 = M2_mpyud_nac_ll_s1
5416 { 1786, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1786 = M2_vmac2
5420 { 1790, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1790 = M2_vmac2s_s0
5421 { 1791, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1791 = M2_vmac2s_s1
5422 { 1792, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1792 = M2_vmac2su_s0
5423 { 1793, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo195, -1 ,nullptr }, // Inst #1793 = M2_vmac2su_s1
5471 { 1841, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1841 = M4_pmpyw_acc
5473 { 1843, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1843 = M4_vpmpyh_acc
5488 { 1858, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1858 = M5_vmacbsu
5489 { 1859, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1859 = M5_vmacbuu