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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3630 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
3640 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
3644 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
3656 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
3717 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #87 = G_INTRINSIC
3718 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
3781 { 151, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #151 = G_BR
3829 { 199, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #199 = DUPLEX_Pseudo
3830 { 200, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList5, ImplicitList6, OperandInfo2, -1 ,nullptr }, // Inst #200 = ENDLOOP0
3831 { 201, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList7, ImplicitList8, OperandInfo2, -1 ,nullptr }, // Inst #201 = ENDLOOP01
3832 { 202, 1, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList9, ImplicitList10, OperandInfo2, -1 ,nullptr }, // Inst #202 = ENDLOOP1
3840 { 210, 1, 0, 4, 17, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #210 = J2_trap1_noregmap
3918 { 288, 1, 0, 4, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800029ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #288 = PS_call_nr
3948 { 318, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #318 = PS_tailcall_i
4027 { 397, 1, 0, 4, 57, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #397 = S6_allocframe_to_raw
4568 { 938, 1, 0, 4, 79, 0, 0x23ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #938 = A4_ext
4688 { 1058, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, nullptr, ImplicitList21, OperandInfo2, -1 ,nullptr }, // Inst #1058 = CALLProfile
4770 { 1140, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200005b10800024ULL, ImplicitList3, ImplicitList24, OperandInfo2, -1 ,nullptr }, // Inst #1140 = J2_call
4776 { 1146, 1, 0, 4, 105, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x5b10800024ULL, nullptr, ImplicitList19, OperandInfo2, -1 ,nullptr }, // Inst #1146 = J2_jump
4810 { 1180, 1, 0, 4, 113, 0, 0xa4ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1180 = J2_pause
4817 { 1187, 1, 0, 4, 116, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xa4ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1187 = J2_trap0
5498 { 1868, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, nullptr, ImplicitList37, OperandInfo2, -1 ,nullptr }, // Inst #1868 = PS_call_stk
5521 { 1891, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1891 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4
5522 { 1892, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1892 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT
5523 { 1893, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1893 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
5524 { 1894, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1894 = RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
5525 { 1895, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1895 = RESTORE_DEALLOC_RET_JMP_V4
5526 { 1896, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList38, OperandInfo2, -1 ,nullptr }, // Inst #1896 = RESTORE_DEALLOC_RET_JMP_V4_EXT
5527 { 1897, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb11800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1897 = RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
5528 { 1898, 1, 0, 4, 105, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0xb10800024ULL, nullptr, ImplicitList39, OperandInfo2, -1 ,nullptr }, // Inst #1898 = RESTORE_DEALLOC_RET_JMP_V4_PIC
6003 { 2373, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, ImplicitList41, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2373 = SAVE_REGISTERS_CALL_V4
6004 { 2374, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, ImplicitList41, ImplicitList30, OperandInfo2, -1 ,nullptr }, // Inst #2374 = SAVE_REGISTERS_CALL_V4STK
6005 { 2375, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, ImplicitList41, ImplicitList30, OperandInfo2, -1 ,nullptr }, // Inst #2375 = SAVE_REGISTERS_CALL_V4STK_EXT
6006 { 2376, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, ImplicitList41, ImplicitList42, OperandInfo2, -1 ,nullptr }, // Inst #2376 = SAVE_REGISTERS_CALL_V4STK_EXT_PIC
6007 { 2377, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, ImplicitList41, ImplicitList42, OperandInfo2, -1 ,nullptr }, // Inst #2377 = SAVE_REGISTERS_CALL_V4STK_PIC
6008 { 2378, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, ImplicitList41, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2378 = SAVE_REGISTERS_CALL_V4_EXT
6009 { 2379, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, ImplicitList41, ImplicitList43, OperandInfo2, -1 ,nullptr }, // Inst #2379 = SAVE_REGISTERS_CALL_V4_EXT_PIC
6010 { 2380, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, ImplicitList41, ImplicitList43, OperandInfo2, -1 ,nullptr }, // Inst #2380 = SAVE_REGISTERS_CALL_V4_PIC
6031 { 2401, 1, 0, 4, 180, 0|(1ULL<<MCID::MayStore), 0x8c000000002bULL, ImplicitList50, ImplicitList51, OperandInfo2, -1 ,nullptr }, // Inst #2401 = SS2_allocframe
6574 { 2944, 1, 0, 4, 256, 0, 0xaULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2944 = V6_vwhist128m