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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3957 { 327, 4, 1, 4, 42, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #327 = PS_vmulw_acc
4531 { 901, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #901 = A2_vraddub_acc
4533 { 903, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #903 = A2_vrsadub_acc
5214 { 1584, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1584 = M2_mmachs_rs0
5215 { 1585, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1585 = M2_mmachs_rs1
5216 { 1586, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1586 = M2_mmachs_s0
5217 { 1587, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1587 = M2_mmachs_s1
5218 { 1588, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1588 = M2_mmacls_rs0
5219 { 1589, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1589 = M2_mmacls_rs1
5220 { 1590, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1590 = M2_mmacls_s0
5221 { 1591, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1591 = M2_mmacls_s1
5222 { 1592, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1592 = M2_mmacuhs_rs0
5223 { 1593, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1593 = M2_mmacuhs_rs1
5224 { 1594, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1594 = M2_mmacuhs_s0
5225 { 1595, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1595 = M2_mmacuhs_s1
5226 { 1596, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1596 = M2_mmaculs_rs0
5227 { 1597, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1597 = M2_mmaculs_rs1
5228 { 1598, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1598 = M2_mmaculs_s0
5229 { 1599, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1599 = M2_mmaculs_s1
5404 { 1774, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1774 = M2_vcmac_s0_sat_i
5405 { 1775, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1775 = M2_vcmac_s0_sat_r
5410 { 1780, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1780 = M2_vdmacs_s0
5411 { 1781, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1781 = M2_vdmacs_s1
5417 { 1787, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1787 = M2_vmac2es
5418 { 1788, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1788 = M2_vmac2es_s0
5419 { 1789, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1789 = M2_vmac2es_s1
5434 { 1804, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1804 = M2_vrcmaci_s0
5435 { 1805, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1805 = M2_vrcmaci_s0c
5436 { 1806, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1806 = M2_vrcmacr_s0
5437 { 1807, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1807 = M2_vrcmacr_s0c
5442 { 1812, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1812 = M2_vrcmpys_acc_s1_h
5443 { 1813, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1813 = M2_vrcmpys_acc_s1_l
5448 { 1818, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1818 = M2_vrmac_s0
5474 { 1844, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1844 = M4_vrmpyeh_acc_s0
5475 { 1845, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1845 = M4_vrmpyeh_acc_s1
5478 { 1848, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1848 = M4_vrmpyoh_acc_s0
5479 { 1849, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1849 = M4_vrmpyoh_acc_s1
5485 { 1855, 4, 1, 4, 142, 0, 0x20000000000002dULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1855 = M4_xor_xacc
5486 { 1856, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #1856 = M5_vdmacbsu
5492 { 1862, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1862 = M5_vrmacbsu
5493 { 1863, 4, 1, 4, 32, 0, 0x200000000000026ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1863 = M5_vrmacbuu
5614 { 1984, 4, 1, 4, 142, 0, 0x20000000000002dULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1984 = S2_insertp_rp