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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 4031 { 401, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #401 = V6_MAP_equb_and
4032 { 402, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #402 = V6_MAP_equb_ior
4033 { 403, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #403 = V6_MAP_equb_xor
4035 { 405, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #405 = V6_MAP_equh_and
4036 { 406, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #406 = V6_MAP_equh_ior
4037 { 407, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #407 = V6_MAP_equh_xor
4039 { 409, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #409 = V6_MAP_equw_and
4040 { 410, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x100000000000027ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #410 = V6_MAP_equw_ior
4041 { 411, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #411 = V6_MAP_equw_xor
6300 { 2670, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2670 = V6_veqb_and
6301 { 2671, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2671 = V6_veqb_or
6302 { 2672, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2672 = V6_veqb_xor
6304 { 2674, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2674 = V6_veqh_and
6305 { 2675, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2675 = V6_veqh_or
6306 { 2676, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2676 = V6_veqh_xor
6308 { 2678, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2678 = V6_veqw_and
6309 { 2679, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2679 = V6_veqw_or
6310 { 2680, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2680 = V6_veqw_xor
6318 { 2688, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2688 = V6_vgtb_and
6319 { 2689, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2689 = V6_vgtb_or
6320 { 2690, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2690 = V6_vgtb_xor
6322 { 2692, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2692 = V6_vgth_and
6323 { 2693, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2693 = V6_vgth_or
6324 { 2694, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2694 = V6_vgth_xor
6326 { 2696, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2696 = V6_vgtub_and
6327 { 2697, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2697 = V6_vgtub_or
6328 { 2698, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2698 = V6_vgtub_xor
6330 { 2700, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2700 = V6_vgtuh_and
6331 { 2701, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2701 = V6_vgtuh_or
6332 { 2702, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2702 = V6_vgtuh_xor
6334 { 2704, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2704 = V6_vgtuw_and
6335 { 2705, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2705 = V6_vgtuw_or
6336 { 2706, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2706 = V6_vgtuw_xor
6338 { 2708, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2708 = V6_vgtw_and
6339 { 2709, 4, 1, 4, 208, 0, 0x100000000000010ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2709 = V6_vgtw_or
6340 { 2710, 4, 1, 4, 208, 0, 0x10ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2710 = V6_vgtw_xor