reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc

 8165   { 0 /*  */, Hexagon::S2_lsr_i_r, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

32420 /* 62755*/        OPC_MorphNodeTo1, TARGET_VAL(Hexagon::S2_lsr_i_r), 0,
32427 /* 62767*/        OPC_MorphNodeTo1, TARGET_VAL(Hexagon::S2_lsr_i_r), 0,
66217 /*127327*/          OPC_MorphNodeTo1, TARGET_VAL(Hexagon::S2_lsr_i_r), 0,

gen/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc

 5917     case Hexagon::S2_lsr_i_r:

lib/Target/Hexagon/HexagonBitSimplify.cpp

 1163     case S2_lsr_i_r:
 2061   } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) {
 2062     if (validateReg(L, Hexagon::S2_lsr_i_r, 1)) {
 2064       BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
 2983     case Hexagon::S2_lsr_i_r:

lib/Target/Hexagon/HexagonBitTracker.cpp

  661     case S2_lsr_i_r:

lib/Target/Hexagon/HexagonHardwareLoops.cpp

  975     const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);

lib/Target/Hexagon/HexagonSplitDouble.cpp

  804                            : (Signed ? S2_asr_i_r : S2_lsr_i_r);