|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc20379 /* 38897*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
20699 /* 39493*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21745 /* 41459*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21779 /* 41535*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21825 /* 41633*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21859 /* 41709*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21908 /* 41812*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21945 /* 41893*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
21996 /* 42002*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22030 /* 42078*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22078 /* 42180*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22112 /* 42256*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22163 /* 42363*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22200 /* 42444*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22264 /* 42579*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22308 /* 42672*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22364 /* 42787*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22408 /* 42880*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22467 /* 43000*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22514 /* 43098*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22575 /* 43224*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22619 /* 43317*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22677 /* 43436*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22721 /* 43529*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22782 /* 43653*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22829 /* 43751*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22888 /* 43869*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
22908 /* 43928*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
26022 /* 49962*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
26029 /* 49988*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
26565 /* 51019*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
26572 /* 51045*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
27164 /* 52193*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
27184 /* 52252*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
31417 /* 60885*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
31438 /* 60947*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
51910 /* 97803*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
52120 /* 98238*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
52514 /* 99100*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
52619 /* 99353*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
53993 /*101961*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
54013 /*102020*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55889 /*105599*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55905 /*105643*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55921 /*105687*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55945 /*105745*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55960 /*105785*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
55975 /*105825*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56010 /*105899*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56026 /*105943*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56042 /*105987*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56528 /*106947*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56543 /*106988*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56558 /*107029*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56591 /*107100*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56606 /*107141*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56621 /*107182*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56822 /*107649*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56838 /*107693*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56854 /*107737*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56870 /*107781*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56886 /*107825*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56902 /*107869*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56918 /*107913*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
56934 /*107957*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57112 /*108364*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57127 /*108405*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57142 /*108446*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57157 /*108487*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57172 /*108528*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57187 /*108569*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57202 /*108610*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57217 /*108651*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57424 /*109129*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57440 /*109173*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57456 /*109217*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57472 /*109261*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57488 /*109305*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57504 /*109349*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57520 /*109393*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57536 /*109437*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57719 /*109856*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57734 /*109897*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57749 /*109938*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57764 /*109979*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57779 /*110020*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57794 /*110061*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57809 /*110102*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
57824 /*110143*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58222 /*110987*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58238 /*111031*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58254 /*111075*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58270 /*111119*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58286 /*111163*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58301 /*111203*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58316 /*111243*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58841 /*112293*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58856 /*112334*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58871 /*112375*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
58886 /*112416*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
59369 /*113385*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
59384 /*113427*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
59399 /*113469*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63520 /*121662*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63537 /*121710*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63605 /*121870*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63622 /*121918*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63687 /*122066*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63739 /*122173*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63756 /*122221*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63823 /*122379*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
63840 /*122427*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64483 /*123827*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64493 /*123858*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64544 /*123962*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64554 /*123992*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64698 /*124270*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
64814 /*124617*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67173 /*129021*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67328 /*129377*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67389 /*129552*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67413 /*129624*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67585 /*130155*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67604 /*130227*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67627 /*130306*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67651 /*130389*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67701 /*130568*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67828 /*131018*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67852 /*131100*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
67880 /*131197*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
68405 /*132437*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
68431 /*132511*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70018 /*135660*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70205 /*136131*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70490 /*136764*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70565 /*136918*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70669 /*137209*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70744 /*137363*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70848 /*137654*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
70923 /*137808*/ OPC_EmitInteger, MVT::i32, Hexagon::DoubleRegsRegClassID,
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3376 static const MCOperandInfo OperandInfo36[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3376 static const MCOperandInfo OperandInfo36[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3380 static const MCOperandInfo OperandInfo40[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3380 static const MCOperandInfo OperandInfo40[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3381 static const MCOperandInfo OperandInfo41[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3381 static const MCOperandInfo OperandInfo41[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3382 static const MCOperandInfo OperandInfo42[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3383 static const MCOperandInfo OperandInfo43[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3383 static const MCOperandInfo OperandInfo43[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3383 static const MCOperandInfo OperandInfo43[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3384 static const MCOperandInfo OperandInfo44[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3390 static const MCOperandInfo OperandInfo50[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3390 static const MCOperandInfo OperandInfo50[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3391 static const MCOperandInfo OperandInfo51[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3392 static const MCOperandInfo OperandInfo52[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3397 static const MCOperandInfo OperandInfo57[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3397 static const MCOperandInfo OperandInfo57[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3397 static const MCOperandInfo OperandInfo57[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3398 static const MCOperandInfo OperandInfo58[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3398 static const MCOperandInfo OperandInfo58[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3399 static const MCOperandInfo OperandInfo59[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3403 static const MCOperandInfo OperandInfo63[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3404 static const MCOperandInfo OperandInfo64[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3405 static const MCOperandInfo OperandInfo65[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3405 static const MCOperandInfo OperandInfo65[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3405 static const MCOperandInfo OperandInfo65[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3409 static const MCOperandInfo OperandInfo69[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3410 static const MCOperandInfo OperandInfo70[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3415 static const MCOperandInfo OperandInfo75[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3415 static const MCOperandInfo OperandInfo75[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3415 static const MCOperandInfo OperandInfo75[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3415 static const MCOperandInfo OperandInfo75[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3420 static const MCOperandInfo OperandInfo80[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3420 static const MCOperandInfo OperandInfo80[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3421 static const MCOperandInfo OperandInfo81[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3423 static const MCOperandInfo OperandInfo83[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3461 static const MCOperandInfo OperandInfo121[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3462 static const MCOperandInfo OperandInfo122[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3472 static const MCOperandInfo OperandInfo132[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3473 static const MCOperandInfo OperandInfo133[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3480 static const MCOperandInfo OperandInfo140[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3480 static const MCOperandInfo OperandInfo140[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3481 static const MCOperandInfo OperandInfo141[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
3481 static const MCOperandInfo OperandInfo141[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
3481 static const MCOperandInfo OperandInfo141[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
3482 static const MCOperandInfo OperandInfo142[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3483 static const MCOperandInfo OperandInfo143[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3484 static const MCOperandInfo OperandInfo144[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3485 static const MCOperandInfo OperandInfo145[] = { { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3486 static const MCOperandInfo OperandInfo146[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3487 static const MCOperandInfo OperandInfo147[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3488 static const MCOperandInfo OperandInfo148[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3488 static const MCOperandInfo OperandInfo148[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3488 static const MCOperandInfo OperandInfo148[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3488 static const MCOperandInfo OperandInfo148[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3489 static const MCOperandInfo OperandInfo149[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3489 static const MCOperandInfo OperandInfo149[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3491 static const MCOperandInfo OperandInfo151[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3493 static const MCOperandInfo OperandInfo153[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3500 static const MCOperandInfo OperandInfo160[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3503 static const MCOperandInfo OperandInfo163[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3505 static const MCOperandInfo OperandInfo165[] = { { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3512 static const MCOperandInfo OperandInfo172[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3512 static const MCOperandInfo OperandInfo172[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3513 static const MCOperandInfo OperandInfo173[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3513 static const MCOperandInfo OperandInfo173[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3514 static const MCOperandInfo OperandInfo174[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3514 static const MCOperandInfo OperandInfo174[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3515 static const MCOperandInfo OperandInfo175[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3515 static const MCOperandInfo OperandInfo175[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3519 static const MCOperandInfo OperandInfo179[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3520 static const MCOperandInfo OperandInfo180[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3521 static const MCOperandInfo OperandInfo181[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3523 static const MCOperandInfo OperandInfo183[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3524 static const MCOperandInfo OperandInfo184[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3525 static const MCOperandInfo OperandInfo185[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3525 static const MCOperandInfo OperandInfo185[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3526 static const MCOperandInfo OperandInfo186[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3526 static const MCOperandInfo OperandInfo186[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3528 static const MCOperandInfo OperandInfo188[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3529 static const MCOperandInfo OperandInfo189[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3531 static const MCOperandInfo OperandInfo191[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3532 static const MCOperandInfo OperandInfo192[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3535 static const MCOperandInfo OperandInfo195[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3535 static const MCOperandInfo OperandInfo195[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3540 static const MCOperandInfo OperandInfo200[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3541 static const MCOperandInfo OperandInfo201[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3541 static const MCOperandInfo OperandInfo201[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3541 static const MCOperandInfo OperandInfo201[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3542 static const MCOperandInfo OperandInfo202[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3543 static const MCOperandInfo OperandInfo203[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3543 static const MCOperandInfo OperandInfo203[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3544 static const MCOperandInfo OperandInfo204[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3545 static const MCOperandInfo OperandInfo205[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3545 static const MCOperandInfo OperandInfo205[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3545 static const MCOperandInfo OperandInfo205[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3548 static const MCOperandInfo OperandInfo208[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3549 static const MCOperandInfo OperandInfo209[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3553 static const MCOperandInfo OperandInfo213[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3554 static const MCOperandInfo OperandInfo214[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3555 static const MCOperandInfo OperandInfo215[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3556 static const MCOperandInfo OperandInfo216[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3557 static const MCOperandInfo OperandInfo217[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3557 static const MCOperandInfo OperandInfo217[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3557 static const MCOperandInfo OperandInfo217[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3558 static const MCOperandInfo OperandInfo218[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3558 static const MCOperandInfo OperandInfo218[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3558 static const MCOperandInfo OperandInfo218[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3563 static const MCOperandInfo OperandInfo223[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3564 static const MCOperandInfo OperandInfo224[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3567 static const MCOperandInfo OperandInfo227[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3568 static const MCOperandInfo OperandInfo228[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3569 static const MCOperandInfo OperandInfo229[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3569 static const MCOperandInfo OperandInfo229[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3570 static const MCOperandInfo OperandInfo230[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3570 static const MCOperandInfo OperandInfo230[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3570 static const MCOperandInfo OperandInfo230[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3612 static const MCOperandInfo OperandInfo272[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3618 static const MCOperandInfo OperandInfo278[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 1293 { DoubleRegs, DoubleRegsBits, 247, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 1, true },
2803 &HexagonMCRegisterClasses[DoubleRegsRegClassID],
lib/Target/Hexagon/HexagonBitSimplify.cpp 416 case Hexagon::DoubleRegsRegClassID:
911 case Hexagon::DoubleRegsRegClassID:
2228 SRC != Hexagon::DoubleRegsRegClassID)
2269 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID)
2731 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) {
lib/Target/Hexagon/HexagonBitTracker.cpp 98 case Hexagon::DoubleRegsRegClassID:
145 case Hexagon::DoubleRegsRegClassID:
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 785 case Hexagon::DoubleRegsRegClassID:
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 779 CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, dl, MVT::i32),
1485 CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, dl, MVT::i32),
lib/Target/Hexagon/HexagonRegisterInfo.cpp 80 case DoubleRegsRegClassID:
318 case Hexagon::DoubleRegsRegClassID:
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 457 Hexagon::DoubleRegsRegClassID) {