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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/MSP430/MSP430GenAsmMatcher.inc 534 case MCK_IndReg: {
612 case MCK_IndReg: return "MCK_IndReg";
719 { 10 /* add */, MSP430::ADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
720 { 10 /* add */, MSP430::ADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
731 { 14 /* add.b */, MSP430::ADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
732 { 14 /* add.b */, MSP430::ADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
743 { 20 /* addc */, MSP430::ADDC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
744 { 20 /* addc */, MSP430::ADDC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
755 { 25 /* addc.b */, MSP430::ADDC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
756 { 25 /* addc.b */, MSP430::ADDC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
767 { 32 /* and */, MSP430::AND16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
768 { 32 /* and */, MSP430::AND16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
779 { 36 /* and.b */, MSP430::AND8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
780 { 36 /* and.b */, MSP430::AND8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
791 { 42 /* bic */, MSP430::BIC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
792 { 42 /* bic */, MSP430::BIC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
803 { 46 /* bic.b */, MSP430::BIC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
804 { 46 /* bic.b */, MSP430::BIC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
815 { 52 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
816 { 52 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
827 { 56 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
828 { 56 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
839 { 62 /* bit */, MSP430::BIT16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
840 { 62 /* bit */, MSP430::BIT16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
851 { 66 /* bit.b */, MSP430::BIT8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
852 { 66 /* bit.b */, MSP430::BIT8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
862 { 75 /* call */, MSP430::CALLn, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
878 { 105 /* cmp */, MSP430::CMP16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
879 { 105 /* cmp */, MSP430::CMP16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
890 { 109 /* cmp.b */, MSP430::CMP8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
891 { 109 /* cmp.b */, MSP430::CMP8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
906 { 127 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
907 { 127 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
918 { 132 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
919 { 132 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
954 { 209 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
955 { 209 /* mov */, MSP430::MOV16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
965 { 213 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
966 { 213 /* mov.b */, MSP430::MOV8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
987 { 268 /* rra */, MSP430::RRA16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
991 { 272 /* rra.b */, MSP430::RRA8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
995 { 278 /* rrc */, MSP430::RRC16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
999 { 282 /* rrc.b */, MSP430::RRC8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1015 { 313 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1016 { 313 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1027 { 317 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1028 { 317 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1039 { 323 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1040 { 323 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1051 { 328 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1052 { 328 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1058 { 335 /* swpb */, MSP430::SWPB16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1062 { 340 /* sxt */, MSP430::SEXT16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1075 { 354 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1076 { 354 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1087 { 358 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1088 { 358 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },