reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6045 { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 6796 { 5430 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6802 { 5444 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6831 { 5538 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6836 { 5552 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6858 { 5586 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6886 { 5627 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7410 { 7638 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 7504 { 7916 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7514 { 7927 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7609 { 8082 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7906 { 9229 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7971 { 9403 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, 7973 { 9410 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, 9161 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10066 { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10067 { 5430 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10078 { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10079 { 5444 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10130 { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10131 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10140 { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10141 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10170 { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10171 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10214 { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10215 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10871 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10986 { 7916 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 10987 { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11006 { 7927 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11007 { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11110 { 8082 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11111 { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11423 { 9229 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, 11424 { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },