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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5464 { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5534 { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5536 { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5575 { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5577 { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5605 { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5607 { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5730 { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6099 { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6119 { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6319 { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6345 { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6502 { 3937 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, },
6504 { 3937 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6524 { 3969 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, },
6526 { 3969 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6761 { 5356 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6764 { 5362 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6774 { 5369 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6776 { 5369 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, },
6791 { 5422 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6862 { 5590 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6897 { 5660 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
7512 { 7923 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
8343 { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8411 { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8413 { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8451 { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8453 { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8481 { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8483 { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8688 { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9226 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9246 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9505 { 3229 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9533 { 3309 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9752 { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9759 { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10023 { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10024 { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10029 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10030 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10041 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10043 { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10058 { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10176 { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10236 { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
11002 { 7923 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
11003 { 7923 /* scd */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6 },