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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5617 { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, },
5636 { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5638 { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5651 { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5662 { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5664 { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5672 { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5679 { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5688 { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5692 { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5706 { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5708 { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5742 { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5744 { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5750 { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5757 { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5766 { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5770 { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5781 { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5800 { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5802 { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5808 { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5815 { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
6041 { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
6326 { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6353 { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6816 { 5482 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6882 { 5617 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7051 { 6375 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7063 { 6450 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7194 { 6829 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7197 { 6833 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7203 { 6838 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7255 { 7049 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7406 { 7633 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7519 { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7523 { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7531 { 7953 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7662 { 8320 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, },
7664 { 8320 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, },
7902 { 9219 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
8499 { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8528 { 848 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8529 { 848 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8532 { 863 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8533 { 863 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8550 { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8551 { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8570 { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8571 { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8574 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8575 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8590 { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8591 { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8604 { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8605 { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8622 { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8623 { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8630 { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8631 { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8658 { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8659 { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8662 { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8663 { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8710 { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8711 { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8714 { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8715 { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8726 { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8727 { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8740 { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8741 { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8758 { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8759 { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8766 { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8767 { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8784 { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8785 { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8812 { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8813 { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8816 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8817 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8828 { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8829 { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8842 { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8843 { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9157 { 1962 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9513 { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9542 { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10104 { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10105 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10206 { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10207 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10445 { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10457 { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10658 { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10661 { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10667 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10727 { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10867 { 7633 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11022 { 7953 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11023 { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11415 { 9219 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11416 { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },