reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5416 { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5438 { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6053 { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6235 { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6239 { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 6250 { 3052 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6261 { 3094 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6331 { 3233 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6619 { 4502 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6813 { 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6990 { 6081 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7066 { 6455 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7156 { 6706 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 7208 { 6842 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7269 { 7086 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7428 { 7688 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7473 { 7800 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7480 { 7820 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7528 { 7948 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7738 { 8543 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7819 { 8835 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 8006 { 9489 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 8301 { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 8323 { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9173 { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9174 { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9404 { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9405 { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9412 { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9413 { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9431 { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9432 { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9450 { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9451 { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9519 { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9883 { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 9884 { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10098 { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10099 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10367 { 6081 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10368 { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10460 { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10599 { 6706 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10600 { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10672 { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10740 { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10896 { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10944 { 7800 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10945 { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10953 { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11016 { 7948 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11017 { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11239 { 8543 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11319 { 8835 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11506 { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11507 { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },