reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2518 case MCK_ConstantSImm10_0: return true; 2559 case MCK_ConstantSImm10_0: return true; 2599 case MCK_ConstantSImm10_0: return true; 2639 case MCK_ConstantSImm10_0: return true; 2678 case MCK_ConstantSImm10_0: return true; 2716 case MCK_ConstantSImm10_0: return true; 2753 case MCK_ConstantSImm10_0: return true; 2789 case MCK_ConstantSImm10_0: return true; 2824 case MCK_ConstantSImm10_0: return true; 2858 case MCK_ConstantSImm10_0: return true; 2891 case MCK_ConstantSImm10_0: return true; 2923 case MCK_ConstantSImm10_0: return true; 2954 case MCK_ConstantSImm10_0: return true; 2984 case MCK_ConstantSImm10_0: return true; 3013 case MCK_ConstantSImm10_0: return true; 3041 case MCK_ConstantSImm10_0: return true; 3068 case MCK_ConstantSImm10_0: return true; 3094 case MCK_ConstantSImm10_0: return true; 3119 case MCK_ConstantSImm10_0: return true; 3143 case MCK_ConstantSImm10_0: return true; 3166 case MCK_ConstantSImm10_0: return true; 3188 case MCK_ConstantSImm10_0: return true; 3209 case MCK_ConstantSImm10_0: return true; 3229 case MCK_ConstantSImm10_0: return true; 3248 case MCK_ConstantSImm10_0: return true; 3264 case MCK_ConstantSImm10_0: 4031 case MCK_ConstantSImm10_0: { 4747 case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0"; 6820 { 5492 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6821 { 5498 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6822 { 5504 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6823 { 5510 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 7441 { 7713 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7442 { 7713 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7573 { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7574 { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7727 { 8470 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7728 { 8470 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },