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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 2483 case MCK_MemOffsetSimm9:
3730 case MCK_MemOffsetSimm9: {
4712 case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9";
6041 { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
6045 { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
6046 { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
6796 { 5430 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6802 { 5444 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6831 { 5538 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6832 { 5538 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6836 { 5552 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6837 { 5552 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6850 { 5579 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6851 { 5579 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6852 { 5579 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6858 { 5586 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6859 { 5586 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6886 { 5627 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6887 { 5627 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6890 { 5635 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6891 { 5635 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6901 { 5669 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6902 { 5669 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7406 { 7633 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7410 { 7638 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7411 { 7638 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7504 { 7916 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7505 { 7916 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7506 { 7920 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7507 { 7920 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7508 { 7920 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7512 { 7923 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
7514 { 7927 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7515 { 7927 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7609 { 8082 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7610 { 8082 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7906 { 9229 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7907 { 9229 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7910 { 9237 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7911 { 9237 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7919 { 9266 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7920 { 9266 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
9157 { 1962 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9161 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
9162 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10067 { 5430 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10079 { 5444 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10131 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10133 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10141 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10143 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10155 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10157 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10159 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 },
10171 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10173 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10215 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10217 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10223 { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10225 { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10243 { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10245 { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10867 { 7633 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10871 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10872 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10987 { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10989 { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10991 { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10993 { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10995 { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 },
11003 { 7923 /* scd */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6 },
11007 { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11009 { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11111 { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11113 { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11424 { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11426 { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11432 { 9237 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11434 { 9237 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11450 { 9266 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11452 { 9266 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11654 case MCK_MemOffsetSimm9: