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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 6787 { 5411 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
6814 { 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
gen/lib/Target/Mips/MipsGenDAGISel.inc 1149 /* 2030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC164), 0|OPFL_Chain|OPFL_MemRefs,
1258 /* 2227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC164), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/Mips/MipsGenInstrInfo.inc16792 { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },
16792 { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 6552 case Mips::LDC164:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 3479 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
lib/Target/Mips/MipsInstructionSelector.cpp 205 return isStore ? Mips::SDC164 : Mips::LDC164;
lib/Target/Mips/MipsSEInstrInfo.cpp 50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
354 Opc = Mips::LDC164;