|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4804 { 484, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #484 = B
4811 { 491, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #491 = BAsmE
4812 { 492, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #492 = BAsmH
4813 { 493, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #493 = BAsmHE
4814 { 494, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #494 = BAsmL
4815 { 495, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #495 = BAsmLE
4816 { 496, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #496 = BAsmLH
4817 { 497, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #497 = BAsmM
4818 { 498, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #498 = BAsmNE
4819 { 499, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #499 = BAsmNH
4820 { 500, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #500 = BAsmNHE
4821 { 501, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #501 = BAsmNL
4822 { 502, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #502 = BAsmNLE
4823 { 503, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #503 = BAsmNLH
4824 { 504, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #504 = BAsmNM
4825 { 505, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #505 = BAsmNO
4826 { 506, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #506 = BAsmNP
4827 { 507, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #507 = BAsmNZ
4828 { 508, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #508 = BAsmO
4829 { 509, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #509 = BAsmP
4830 { 510, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #510 = BAsmZ
4839 { 519, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #519 = BI
4840 { 520, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #520 = BIAsmE
4841 { 521, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #521 = BIAsmH
4842 { 522, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #522 = BIAsmHE
4843 { 523, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #523 = BIAsmL
4844 { 524, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #524 = BIAsmLE
4845 { 525, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #525 = BIAsmLH
4846 { 526, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #526 = BIAsmM
4847 { 527, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #527 = BIAsmNE
4848 { 528, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #528 = BIAsmNH
4849 { 529, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #529 = BIAsmNHE
4850 { 530, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #530 = BIAsmNL
4851 { 531, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #531 = BIAsmNLE
4852 { 532, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #532 = BIAsmNLH
4853 { 533, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #533 = BIAsmNM
4854 { 534, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #534 = BIAsmNO
4855 { 535, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #535 = BIAsmNP
4856 { 536, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #536 = BIAsmNZ
4857 { 537, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #537 = BIAsmO
4858 { 538, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #538 = BIAsmP
4859 { 539, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #539 = BIAsmZ